This invention relates generally to the field of data memories, and, more specifically, to memories of the type that store data as levels of electronic charge, including, but not limited to, flash electrically erasable and programmable read-only-memories (flash EEPROMs) utilizing either conductive floating gates or dielectric material as charge storage elements.
It is common in current commercial products for each storage element of a flash EEPROM array to store a single bit of data by operating in a binary mode, where two ranges of threshold levels of the storage element transistors are defined as storage levels. The threshold levels of transistors correspond to ranges of charge levels stored on their storage elements. In addition to shrinking the size of the memory arrays, the trend is to further increase the density of data storage of such memory arrays by storing more than one bit of data in each storage element transistor. This is accomplished by defining more than two threshold levels as storage states for each storage element transistor, four such states (2 bits of data per storage element) now being included in commercial products. More storage states, such as 16 states (4 data bits) per storage element, are contemplated. Each storage element memory transistor has a certain total range (window) of threshold voltages in which it may practically be operated, and that range is divided into the number of states defined for it plus margins between the states to allow for them to be clearly differentiated from one another.
As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the storage elements decreases. Since the ranges of charge designated for each storage state must necessarily be made narrower and placed closer together as the number of states stored on each memory cell storage element increases, the programming must be performed with an increased degree of precision and the extent of any post-programming shifts in the stored charge levels that can be tolerated, either actual or apparent shifts, is reduced. Actual disturbs to the charge stored in one cell can be created when programming and reading that cell, and when reading, programming and erasing other cells that have some degree of electrical coupling with that cell, such as those in the same column or row, and those sharing a line or node.
Apparent shifts in the stored charge levels occur because of field coupling between storage elements. The degree of this coupling is necessarily increasing as the spaces between memory cell storage elements are being decreased, which is occurring as the result of improvements of integrated circuit manufacturing techniques. The problem occurs most pronouncedly between two groups of adjacent cells that have been programmed at different times. One group of cells is programmed to add a level of charge to their storage elements that corresponds to one set of data. After the second group of cells is programmed with a second set of data, the charge levels read from the storage elements of the first group of cells often appear to be different than programmed because of the effect of the charge on the second group of storage elements being capacitively coupled with the first. This is known as the Yupin effect, and is described in U.S. Pat. No. 5,867,429, which patent is incorporated herein in their entirety by this reference. This patent describes either physically isolating the two groups of storage elements from each other, or taking into account the effect of the charge on the second group of storage elements when reading that of the first group.
According to an application of one aspect of the present invention, in order to overcome the effects on each other of adjacent programmed rows of memory cells, adjacent rows are programmed in two steps. In a first step, a first row of memory cells is programmed with data to a first, intermediate set of threshold levels. After a second adjacent row of memory cells is similarly programmed, the threshold levels of the first row of memory cells are increased to a second, final set of threshold levels. Since the final programming of the first row occurs under the influence of the second row""s initial programming, data read from the first row is not adversely affected by the levels initially programmed into the second row. After a third row adjacent the second row is programmed to the first set of threshold levels, the threshold levels of the second row are increased to the final set. The process is continued for the programming of any additional rows of memory cells having field coupling between adjacent rows.
According to an application of another aspect of the present invention, an identification of the set of levels at which a group, such as a row, of cells has been programmed is stored in a manner to be read along with the programmed group of cells. A group of memory cells is initially read with applied read voltages chosen for optimally reading cells programmed with the most common one of the sets of levels. If the initially read identification shows that the cells were programmed with the other set of levels, however, the group of cells is re-read with applied read voltages corresponding to the other set of levels.
The present invention can be implemented in various types of flash EEPROM cell arrays. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one storage element transistor, with or without a select transistor formed in series with it, or two storage element transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporate herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, 6,091,633, 6,103,573, 6,151,248, 6,426,893, 6,512,,263, and applications Ser. No. 09/925,102, filed Aug. 8, 2001, and Serial No. 09/925,134, filed Aug. 8, 2001.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in a series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells across different series strings. Relevant examples of such arrays and their operation are given in the following U.S. patents and patent application that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,570,315, 5,774,397 and 6,046,935, and 6,522,580. Briefly, two kits of data from different logical pages of incoming data are programmed into one of four states of the individual cells in two steps, first programming a cell into one state according to one bit of data and then, if the data makes it necessary, reprogramming that cell into another one of its states according to the second bit of incoming data.
The above-referenced patents and patent applications describe flash EEPROM systems that use conductive floating gates as memory cell storage elements. Alternatively, flash EEPROM systems with memory cells employing charge trapping dielectric material in place of floating gates are operated in substantially the same way. Examples of this are included in patent application Ser. No. 10/002,696, filed Oct. 31, 2001, Haari et al., entitled xe2x80x9cMulti-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements,xe2x80x9d published as U.S. Ser. No. 2003/0082871 A1 on May 1, 2003 which application is incorporated herein by this reference. Field coupling between dielectric storage elements of adjacent memory cells can also affect the accuracy of the data read from such memory systems.
Additional aspects, features and advantages of the present invention can be had from the following detailed description of exemplary embodiments thereof, which description should be read along with reference to the accompanying drawings.